1. Field of the Invention
The present invention relates generally to devices and methods for driving liquid crystal panels, and particularly to a device and a method for driving an active matrix display type color liquid crystal display panel by using a low speed clock signal. More particularly, the present invention relates to a structure of a liquid crystal panel drive line memory circuit and a drive method thereof for applying a color signal to a series of signal electrodes included in the liquid crystal panel according to a high speed line sequential system.
2. Description of the Related Art
Display devices using a liquid crystal can be driven with low voltage and consequently they are utilized for applications which require low consumption of power. As an example of such applications, there are liquid crystal panels having a matrix arrangement of liquid crystal pixels and to be driven by successively applying a video signal to each liquid crystal pixel to display an image.
FIGS. 1A to 1C show schematically a structure of a conventional active matrix display type color liquid crystal panel.
Referring to FIG. 1A, pixels P.sub.11, P.sub.12, . . . , P.sub.1(N-1), P.sub.1N, . . . , P.sub.M(N-1), P.sub.MN (pixels being generically denoted by the reference character P) are arranged in a matrix of M rows and N columns on a panel (i.e., an active matrix display type color liquid crystal panel) 1 to form a display screen (hereinafter referred to as a screen) 2. A thin film transistor, not shown, (hereinafter referred to as TFT) is provided in each pixel P in a one-to-one correspondence.
As shown in FIG. 1B, each pixel P comprises a TFT.multidot.Tr, a capacitor CA and a liquid crystal element LE. The TFT.multidot.Tr has its gate connected to a scanning line (i.e., a gate line) lx and its source connected to a source line ly. The capacitor CA accumulates signals transmitted from the source line ly through the TFT.multidot.Tr. The liquid crystal element LE transmits or interrupts light in response to a signal potential from the source line ly or the capacitor CA. A color filter, not shown, is disposed on the liquid crystal element LE and a desired color display is obtained through the color filter dependent on the transmission/interruption state of the liquid crystal element LE.
The gates of the TFTs of the respective rows are connected to the corresponding scanning lines (gate lines) l.times.1, l.times.2, l.times.3, . . . l.times.M. A scanning driver 4 activates the scanning lines l.times.1 to l.times.M successively. Thus, the screen 2 is scanned in the vertical direction.
The sources of the TFTs of the respective columns are connected to the corresponding source lines ly1, ly2, . . . , lyN. A color signal is transmitted from a source driver 3 (shown in FIG. 1C) to each of the source lines ly1 to lyN. A plurality of pixels P connected in common to one source line ly constitute a pixel row b1, r2, g3, b4, . . . , r (N-1), gN (a pixel row being generically denoted by a reference character Y) in which an order of colors is preset from the left to the right of the screen 2. The characters b, r, g represent pixels of colors corresponding to color video signals B (blue), R (red), G (green), and the numerals attached to those characters, 1, 2, 3 etc. represent the order of arrangement.
In the following description, a scanning line is generally indicated by the reference characters lx and a source line is generally indicated by the reference characters ly.
Referring to FIG. 1C, the source driving circuit (hereinafter referred to as the source driver) 3 comprises: a shift register 3a including output terminals Q.sub.1 to Q.sub.N corresponding to the number N of source lines ly; an analog switch 3b including switching elements S.sub.1 to S.sub.N provided corresponding to the output terminals Q.sub.1 to Q.sub.N with a one-to-one relation; and an analog sample-and-hold circuit 3c.
The shift register 3a shifts the output in the direction from the output terminal Q.sub.1 to the output terminal Q.sub.N to turn on the switching elements S.sub.1 to S.sub.N successively one by one in the direction shown by the arrow y, whereby the color video signals B, R, G connected to the switching elements S.sub.1 to S.sub.N are applied successively to the analog sample-and-hold circuit 3c.
The analog sample-and-hold circuit 3c holds the color video signals B, R, G accepted in one horizontal period of the screen 2 and outputs those signals individually to the corresponding pixel rows Y through the source lines ly in the subsequent horizontal period. Further at the same time, it accepts in parallel the color signals B, R, G for the subsequent horizontal period.
However, in the above described structure, if the number of pixels of the screen 2 is increased for the purposes of increasing the size of the panel 1 and enhancing the quality of image and the frequency of the clock pulses CK is increased as a result of requirement of high speed scanning, the linearity of the analog sample-and-hold circuit 3c is deteriorated and the consumption of power increases, making it difficult to meet such conditions.
Under the circumstances, it is proposed to use a method in which the screen 2 is divided into blocks and the divided blocks of pluralities of pixel columns are driven by corresponding source drivers, in order to attain high speed scanning by low speed source drivers and to reduce the size of the drive circuit.
FIG. 2 is a block diagram showing an electric construction of a conventional liquid crystal drive circuit. The liquid crystal drive circuit 21 comprises a plurality of source drivers 5 to 8 arranged in peripheral portions of the screen 2, and a plurality of line memory circuits 9 to 14 which supply color video signals R, G, B to the respective source drivers 5 to 8. Each of the line memory circuits 9 to 14 includes an A/D converter, a memory, a multiplexer, a latch circuit, a D/A converter and the like, as described later.
The screen 2 is constructed according to a multiplex matrix system. More specifically, the source lines ly are connected alternately to the upper and lower source drivers 5, 7; 6, 8, and each pixel row Y is divided into two portions, in the horizontal direction, i.e., the first half portion (driven by the source drivers 5, 6) and the second half portion (driven by the source drivers 7, 8). As a result, the screen 2 is formed by four portions, i.e., the respective portions corresponding to the pixel rows Y1 to Y4.
The plurality of source drivers 5 to 8 are arranged around the screen corresponding to the divided pixel rows Y1 to Y4. The color video signals R, G, B applied through the lines 11, 12, 13, respectively, are processed in six line memory circuits 9 to 14 by sequential operation such as analog-to-digital (A/D) conversion, writing, reading, latching and digital-to-analog (D/A) conversion. After that, the processed signals are supplied according to alternate signal strobe operation of the source drivers 5 to 8.
However, in the above described liquid crystal drive circuit, 21, two line memories are required for each of the color signals R, G, B, that is, six line memories in total are required. In addition, the circuit for each line memory is required to comprise, as shown in the block diagram in FIG. 3, an amplifying circuit 9a for the inputted color signal (e.g., B), an A/D converter 9b for digitally converting the inputted color signal, a buffer circuit 9c, a memory 9d for storing the digital data from the buffer circuit 9c, a write address generating circuit 9e and a read address generating circuit 9f for generating write/read addresses for the memory 9d, a multiplexer 9h for switching write/read operations of the memory 9d with prescribed timing and supplying the write address or the read address to the memory 9d, a latch circuit 9i for latching the data read from the memory 9d, a D/A converter 9j for converting the latched digital data to an analog signal, and a buffer 9k provided between the source driver and the D/A converter 9j. The switching of the write/read operations of the memory 9d is carried out under the control of a line memory control circuit 9g through the address multiplexer. In addition, the operation control (such as control of address generation timing) of the write address generating circuit 9e and the read address generating circuit 9f is carried out by the line memory control circuit 9g.
In addition to those line memory circuits 9 to 14 including the various components, it is necessary to further provide delay circuits and the like, not shown, for dissolving inconsistency between the input order of the color signals B, R, G to the line memory circuits 9 to 14 and the color order (the color filter arrangement) b, r, g etc. on a pixel row Y preset in the screen 2, and for changing the order of the data read from the memory 9d according to the order of arrangement of the pixel rows. More specifically, even in the multiplex matrix system, each of the source drivers 5 to 8 has the same structure as shown in FIG. 1C and successively receives and holds a color signal of one color in response to the clock signal CK. On the other hand, each of the line memories 9 to 14 transmits signals to the two source drivers. The signal from one line memory to the source driver (5 or 6) of the first half portion and that to the source driver (7 or 8) of the second half portion are alternately read and, on this occasion, the order of acceptance of the signals provided from the respective line memories 9 to 14 by the source drivers 5 to 8 need to be consistent with the color order of the pixel rows Y. Thus, a delay circuit or the like is required for the output portion of each of the line memories 9 to 14. Accordingly, each of the source drivers 5 to 8 drives only 1/4 of the columns (160 columns in the figure) of the screen 2. In consequence, each of the line memories 9 to 14 can drive the liquid crystal panel at an operation speed equal to 1/2 of that in the case of one memory for each color and each of the source drivers 5 to 8 can drive the panel at an operation speed equal 1/4 of that in the case of one memory for each color. However, the construction of the device is large-sized and complicated.